net: stmmac: dwmac-qcom-ethqos: Restore nominal clk_ptp_ref frequency#619
net: stmmac: dwmac-qcom-ethqos: Restore nominal clk_ptp_ref frequency#619pkrian wants to merge 1 commit into
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
PR #619 — validate-patchPR: #619
Final Summary
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PR #619 — checker-log-analyzerPR: #619
Detailed report: Full report
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shashim-quic
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submit patch upstream and bring it as FROMLIST.
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qli-2.0 GA Critical Fix |
shashim-quic
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Please send the patch upstream and bring as FROMLIST.
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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CRs-Fixed: 4549777 |
…_ref" This reverts commit db845b9. Reason: this change causes the PTP clock to always be in Turbo mode which can cause power KPI regression. Signed-off-by: Kiran Patchala <pkiran@qti.qualcomm.com>
This should be added to PR Body |
Test Matrix
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Test Matrix
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CRs-Fixed : to be added to PR Body |
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
The current implementation configures the PTP reference clock (clk_ptp_ref) to its maximum supported frequency in order to improve timestamp resolution.
While higher clock rates benefit PTP/gPTP accuracy, forcing the PTP reference clock to operate at maximum frequency results in increased power consumption, as the clock remains at this rate irrespective of actual runtime requirements.
On power-sensitive platforms and in use cases where ultra-high timestamp precision is not required, this leads to unnecessary power overhead.
Update the driver to restore the nominal/default clock configuration for clk_ptp_ref, allowing the platform to operate at its baseline frequency (e.g., ~19.2 MHz). This reduces power consumption while maintaining functional correctness for standard PTP operation.
Higher clock frequencies can be enabled through targeted configuration if improved timestamp resolution is required for specific applications